FIG. 2 shows an interline charge-coupled device (CCD) 100. It includes an array of photodiodes 105 connected to vertical CCD 110 (VCCD). The image readout process begins by transferring charge from the photodiodes 105 to the adjacent VCCDs 110. Next, one line at a time is transferred into the horizontal CCD (HCCD) 115. The HCCD serially transfers charge to an output charge-sensing amplifier 120.
FIG. 3 shows a cross section of one interline CCD pixel (with portions of adjacent pixels shown for clarity) of FIG. 2. The photodiode 105 collects photo-generated charge. The charge is confined in the photodiode 105 by a surface pinning p+ implant 230 and a vertical overflow drain 215. Adjacent to the photodiode 105 is the VCCD buried channel 200 built in a p-type well 205 on an n-type substrate 210. Transfer of charge through the VCCD 110 is controlled by the gate 220. The VCCD 110 is shielded from light by an opaque metal layer 225.
The overflow drain 215 is a lightly doped region that has a high degree of manufacturing process variability. The variability is so great that the voltage applied to the substrate 210 must by changed from one image sensor to the next. The substrate voltage controls how much charge can be held in the photodiode 105. If the charge capacity of the photodiode is too high, then a bright spot of light will generate more charge than can be held in the VCCD 110. This causes VCCD blooming. If the charge capacity is too low, then the output amplifier 120 will never reach saturation. The substrate voltage is adjusted for each individual image sensor to optimize the photodiode charge capacity for the best compromise between anti-blooming protection and saturation signal level.
In the past, image sensors have been fabricated with a substrate reference voltage generation circuit. One such circuit is shown in FIG. 1. This circuit contains four fuses, F1 through F4, across a set of resistors in series, R1 through R4. By blowing one or more of the fuses, 16 possible reference voltage combinations V1 are possible. This reference voltage is then connected to the image sensor substrate for optimum anti-blooming and saturation signal.
There are many examples of such voltage divider type fuse or anti-fuse setting circuits for image sensors. They include U.S. Pat. Nos. 5,150,216; 5,867,055; 6,188,092; Japanese Patent 1994153079; and Japanese Patent 2002231889. From the prior art, it is clear that the resistors may be substituted by MOSFET transistors with the gates tied to the transistor source or drain.
One significant deficiency of the prior art is when interline CCDs are used to sum pixels. A simple example is shown in FIG. 4. An interline CCD 100 is shown where two rows of charge from the VCCD 110 is summed into the HCCD 115. This summing process may cause the HCCD 115 charge capacity to be exceeded and result in horizontal charge blooming. It is also possible to sum pixels together in the VCCD to increase frame rates. The pixel summing in the VCCD may exceed the VCCD charge capacity. A well-known solution to prevent blooming of the VCCD or HCCD when summing pixels is to further increase the substrate voltage when in pixel summing mode.
FIG. 5 illustrates the photodiode 105 channel potential vs. depth in the silicon wafer. At the surface, the pinning layer 230 holds the potential at 0V. The n-type photodiode 105 and lightly doped overflow drain 215 form a potential barrier between the photodiode and substrate 210. When the substrate voltage is set to VSub1, the photodiode capacity is larger at ΔVB. When the image sensor changes to pixel summing mode, then the substrate voltage is increased to VSub2 which lowers the photodiode charge capacity to ΔVA.
The problem is how to generate a second reference voltage. The obvious solution would be to place an entire second reference voltage generator on the image sensor like that shown in FIG. 1. This is undesirable because adding more fuses to the image sensor requires extra bond pads for a wafer probe tester to be able to set the fuses. Even if laser trimmed fuses are used, the additional fuses decrease the manufacturing yield of the sensor and increases the chance of debris from the fuse setting process contaminating the pixel array. Therefore, a new circuit is needed that does not increase the number of fuses and can supply more than one reference voltage for pixel summing image sensors.